Xeon Phi Coprocessor (Intel) Codenamed Knights Landing Unvieled
The Xeon Phi Coprocessor family took a step into the spotlight after the opening of the Tianhe-2 Supercomputer, which coupled Intel’s Xeon Processors with the Xeon Phi Coprocessors to outstanding success. Needless to say the landscape of supercomputing might be in for a change. Most Supercomputing clusters use HPC (High Performance Computing) GPGPUS (General Purpose GPUs) such as Nvidia Tesla along with processors,
but the major disadvantage of the GPGPUS is that they require special
code and a CPU to operate. While as the Xeon Phi Coprocessor requires
neither special code nor a CPU to operate and delivers unparalleled
3D Tri-gate Transistors and 512 AVX in Xeon Phi ‘Knights Landing’
The current generation of Intel’s Coprocessor Series Codenamed
Knights Corner is made from a 22nm process and delivers a peak double precision performance of 1.2 Teraflops per Coprocessor. Knights Corner Coprocessors also use the newly integrated Haswell AVX2 instruction set which widens the Integer register to 256 bit. AVX is the instruction set for floating point operations. Though the Knights Corner family uses the 3D Trigate transistors their power is not truly realized yet.
Cue the Knights Landing series of Xeon Phi Coprocessors which will be
constructed with a 14nm process derived from Skylake and Broadwell and
will use a much widened 512 bit AVX instruction set. Intel also promises that the Knights Landing Coprocessors will break the 3 Teraflop Barrier in Double Precision performance! So we can safely assume that the Xeon Phi Coprocessors of the Knights Landing era will finally fully utilize the 3D Tri-gate technology.